1. Technical Field
A chemical mechanical polishing (CMP) slurry for oxide film and a methods for forming a metal line contact plug of a semiconductor device using the same are disclosed. More particularly, the disclosed methods for forming metal line contact plugs can form a stable landing plug poly (LPP) by performing a polishing process of a multi-layer film by using the CMP slurry for oxide film including an HXOn compound (wherein n is an integer from 1 to 4).
2. Description of the Related Art
In order to provide a small, large capacity and highly integrated semiconductor device, after forming a transistor, a bit line and a capacitor for the device, a subsequent process for forming a multi-layer line such as a metal line for electrically connecting the respective elements needs to be performed.
In general, when a subsequent conventional process for forming a metal line is performed, a planarization process must be performed by polishing multiple layers simultaneously by using a single slurry before a deposition process or etching process.
However, when multiple layers are polished by using a single slurry, each layer has a different polishing speed, namely a different polishing selectivity ratio to the slurry, and thus step differences are generated between the layers which is problematic.
Further, polishing residues of each layer and abrasive residues in the slurry tend to fill the upper portion of the interlayer insulating film because of the high step difference generated in the interlayer insulating film due to its higher polishing speed than the other layers. As a result, defects such as bridges between plugs of the device are generated.
The conventional process for the semiconductor device will be explained in detail with reference to the accompanying drawings.
Referring to FIG. 1A, a process for forming a LPP is observed in a section A–A′ of a plan diagram showing a general word line pattern 4.
Referring to FIG. 1B, a conductive layer for word line (not shown) is deposited on a cell area of a semiconductor substrate, namely silicon substrate 1, a hard mask film (i.e., a nitride film not shown) is deposited on the conductive layer for word line at a thickness of t1 (1500 to 3200 Å). Then, word line pattern 4 having a hard mask pattern 3 on a conductive layer pattern 2 for word line is formed by sequentially etching the hard mask film and the conductive layer for word line.
A spacer 5 is formed on the sides of the resulting structure, and an interlayer insulating film 7 is formed on the entire surface of the resulting structure at a thickness of t2 (5000 to 8000 Å). The interlayer insulating film 7 is planarized.
Referring to FIG. 1C, the thickness of the interlayer insulating film 7 decreases from t2 to t4 (4500 to 7500 Å) according to the planarization process (t2>t4).
An etching process for forming a contact hole 8 for plug by using a landing plug contact mask (not shown) is performed on a predetermined portion of the cell region. Here, since the upper portion of the hard mask pattern 3 is also etched, the thickness of the hard mask pattern decreases from the initial thickness t1 to t3 (1000 to 2500 Å) (t1>t3).
Referring to FIG. 1D, a region (a) where the contact hole 8 for plug is not formed and a region (b) where the interlayer insulating film is removed to form the contact hole 8 are formed according to the etching process. It is observed in section B–B′ as shown in FIG. 1E.
Referring to FIG. 1E, a silicon layer 9 is deposited on the entire surface of the resulting structure including the contact hole 8 for plug. Here, the silicon layer 9 has step difference of t5 (1000 to 2000 Å) due to step difference between the regions (a) and (b).
Thereafter, a plug 11 is isolated by a succeeding polishing process. Preferably, a thickness to be removed is greater than t6 (2200 to 3200 Å).
Referring to FIG. 1F, a CMP process is performed on the entire surface of the silicon layer 9 and the interlayer insulating film 7 by using a general slurry for oxide film until the hard mask pattern 3 is exposed, thereby forming the plug 11.
The slurry for oxide film used in the above CMP process is a general CMP slurry for oxide film having pH of 2 to 12 and includes an abrasive such as colloidal or fumed SiO2 or Al2O3.
In general, a slurry having a similar polishing speed among the multi-layers must be used to remove a multi-layer film. However, when the general single slurry for oxide film is used in the conventional CMP process, the polishing speed of the interlayer insulating film has a higher polishing selectivity ratio than that of the word line hard mask film or silicon layer by at least three times.
Therefore, a step difference t7 of 400 to 500 Å (FIG. 1F) is generated between the hard mask nitride film pattern 3 and the silicon layer 9, and a step difference t8 of 460 to 700 Å is generated between the hard mask nitride film pattern 3 and the interlayer insulating film 7 after the polishing process due to differences of the polishing selectivity ratio.
Further, polishing residues of each layer and abrasive residues from the slurry fill in the upper portion of the interlayer insulating film 7 that has a relatively high step difference from the hard mask nitride film pattern 3.
Referring to FIG. 1G, the abrasive residues of the CMP process are filled in the upper portion of the interlayer insulating film 7, to generate “Pinocchio” defects 17. The “Pinocchio” defects 17 are generated during the process for isolating the plug 11 due to dishing of an oxide film having a high polishing selectivity ratio to the nitride film.
The step difference is observed in a section C–C′ (FIG. 1H).
Referring to FIG. 1H, step differences are generated between the hard mask pattern 4 and the silicon layer 9, and between the hard mask pattern 4 and the interlayer insulating film 7 formed in the cell region of the substrate 1 due to differences of the polishing selectivity ratio after the polishing process using the CMP slurry for oxide film.
When the conventional single slurry is used in the CMP process for polishing the multiple layers, the step differences and Pinocchio defects are generated to form a bridge between plugs and increase leakage current. As a result, mis-alignment is generated in a succeeding process, and thus the manufacturing yield is reduced.